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| 14-bit, 80 msps/155 msps, 1.8 v dual serial output analog-to-digital converter (adc) data sheet ad9644 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2012 analog devices, inc. all rights reserved. features jesd204a coded serial digital outputs snr = 73.7 dbfs at 70 mhz and 80 msps snr = 71.7 dbfs at 70 mhz and 155 msps sfdr = 92 dbc at 70 mhz and 80 msps sfdr = 92 dbc at 70 mhz and 155 msps low power: 423 mw at 80 msps, 567 mw at 155 msps 1.8 v supply operation integer 1-to-8 input clock divider if sampling frequencies to 250 mhz ?148.6 dbfs/hz input noise at 180 mhz and 80 msps ?150.3 dbfs/hz input noise at 180 mhz and 155 msps programmable internal adc voltage reference flexible analog input range: 1.4 v p-p to 2.1 v p-p adc clock duty cycle stabilizer serial port control user-configurable, built-in self-test (bist) capability energy-saving power-down modes applications communications diversity radio systems multimode digital receivers (3g and 4g) gsm, edge, w-cdma, lte, cdma2000, wimax, td-scdma i/q demodulation systems smart antenna systems general-purpose software radios broadband data applications ultrasound equipment functional block diagram reference ad9644 14 vin+a a vdd pdwn drvdd drgnd 14 vin+b vin?b dout+a dout+b vin?a vcma vcmb sclk sdio csb pipeline 14-bit adc pipeline 14-bit adc serial port (spi) clk+ clk? 1 to 8 clock divider dsync+a pll dsync+b a gnd sync dout?a dsync?a dout?b dsync?b 0 9180-001 jesd204a 8-bit/10-bit coding, serializer and cml drivers figure 1. 48-lead 7 mm 7 mm lfcsp product highlights 1. an on-chip pll allows users to provide a single adc sampling clock; the pll multiplies the adc sampling clock to produce the corresponding jesd204a data rate clock. 2. the configurable jesd204a output block supports up to 1.6 gbps per channel data rate when using a dedicated data link per adc or 3.2 gbps data rate when using a single shared data link for both adcs. 3. proprietary differential input that maintains excellent snr performance for input frequencies up to 250 mhz. 4. operation from a single 1.8 v power supply. 5. standard serial port interface (spi) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock dcs, power-down, test modes, voltage reference mode, and serial output configuration.
ad9644 data sheet rev. c | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 adc dc specifications ............................................................... 4 adc ac specifications ............................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 8 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 10 thermal characteristics ................................................................ 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical p erformance characteristics ........................................... 13 equivalent circuits ......................................................................... 19 theory of operation ...................................................................... 20 adc architecture ...................................................................... 20 analog input considerations .................................................... 20 voltage reference ....................................................................... 22 clock input considerations ...................................................... 22 channel/chip synchronization ................................................ 24 power dissipation and standby mode .................................... 24 digital outputs ........................................................................... 24 built - in self - test (bist) and output test .................................. 29 built - in self - test (bist) ............................................................ 29 output test modes ..................................................................... 29 serial port interface (spi) .............................................................. 31 configuration using the spi ..................................................... 31 hardware interface ..................................................................... 32 spi accessible features .............................................................. 32 memory map .................................................................................. 33 reading the memory map register table ............................... 33 memory map register table ..................................................... 34 memory map register descriptions ........................................ 38 applications information .............................................................. 42 design guidelines ...................................................................... 42 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43 revision history 1/12 rev. b to rev. c change to general description section ........................................ 3 6 /11 rev. a to rev. b added figure 23 to figure 40; renumbered sequentially ........ 16 changes to clock input considerations section ........................ 22 added figure 61 .............................................................................. 24 changes to digital outputs and timing section ....................... 27 added figure 69 .............................................................................. 28 changes to output test modes section ...................................... 29 changes to spi accessible features section ............................... 32 4 /11 rev. 0 to rev. a added model - 155 ......................................................... throughout changes to features section and figure 1 ..................................... 1 changes to general description section ....................................... 3 changes to table 1 ............................................................................. 4 changes to table 2 ............................................................................. 5 ch anges to table 4 ............................................................................. 8 additions to tpc introductory statement ................................. 13 changes to sp eed grade id bits in table 17 .............................. 31 changes to ordering guide .......................................................... 40 6/10 revision 0: initial version data sheet ad9644 rev. c | page 3 of 44 general description the ad9644 is a dual, 14 - bit, analog - to - digital converter (ad c) with a high speed serial output interface and sampling speeds of either 80 msps or 155 msps . the ad9644 is designed to support communications appli - cations where high performance, combined with low cost, small size, and versatility, is desired. the je sd204a high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. the dual adc core features a multistage, differential pipelined architecture with integrated output error correction logic. ea ch adc features wide bandwidth differential sample - and - hold analog input amplifiers that support a variety of user - selectable input ranges. an integrated voltage reference eases design consid - erations. a duty cycle stabilizer is provided to compensate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. by default , the adc output data is routed directly to the two external jesd204a serial output ports. these outputs are at cml voltage levels . two modes are supported such that output coded data is either sent through one data link or two. (l = 1; f = 4 or l = 2; f = 2). independent synchronization inputs (dsync) are provided for each channel. flexible power - down options allow significant power savings, when desired. programming for setup and control is accomplished using a 3 - wire spi - compatible serial interface. the ad9644 is available in a 48 - lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. ad9644 data sheet rev. c | page 4 of 44 specifications adc dc specification s avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, dcs enabled, unless otherwise noted. table 1. ad9644 - 80 a d9644 - 155 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full 2 10 2 .2 11 mv gain error full ? 7 ? 2.5 +1 ? 6 ? 1.5 + 4 % fsr differe ntial nonlinearity (dnl) 1 full 0.55 0.55 lsb 25c 0.3 0.3 lsb integral nonlinearity (inl) 1 full 1.1 1.25 lsb 25c 0.5 0.5 5 lsb matching characteristic offset error full ? 7 + 1.5 +10 ? 6 + 1.5 + 9 mv gain error full ? 1.5 + 0.6 +2.75 ? 3.1 + 0.75 + 5 % fsr temperature drift offset error full 2 2 ppm/c gain error full 35 144 ppm/c input referred noise 25c 0.7 0.7 lsb rms analog input input span full 1.383 1.75 2.087 1.383 1.75 2.087 v p -p input capacitance 2 full 7 5 pf input resistance full 20 20 k? vcm output level full 0.88 0.9 0.92 0.87 0.9 0.93 v power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current iavdd 1 full 175 190 226 242 ma idrvdd 1 full 60 67 89 97 ma power consumption sine wave input 1 full 423 460 567 610 mw standby power 3 full 85 168 mw power - down power full 15 27 18 27 mw 1 measured wit h a low input frequency, full - scale sine wave. 2 input capacitance refers to the effective capacitance between one differential input pin and agnd. 3 standby power is measured with a dc input and with the clk pins inactive (set to avdd or agnd). data sheet ad9644 rev. c | page 5 of 44 adc ac specification s avdd = 1.8 v, drvd d = 1.8 v, maximum sample rate, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, dcs enabled, unless otherwise noted. table 2. ad9644 - 80 ad9644 - 155 parameter 1 temperature min typ max min typ max unit signal - t o - noise - ratio (snr) f in = 10 mhz 25c 73.8 71.9 dbfs f in = 70 mhz 25c 73.7 71.7 dbfs f in = 180 mhz 25c 72.6 71.4 dbfs ad9644bcpz -80 full 71.8 dbfs ad9644ccpz -80 full 70.0 dbfs ad9644bcpz -155 full 69.8 dbfs f in = 220 mhz 25c 72.0 71.0 dbfs signal - to - noise and distortion (sinad) f in = 10 mhz 25c 72.7 70.8 dbfs f in = 70 mhz 25c 72.6 70.7 dbfs f in = 180 mhz 25c 71.5 70. 3 dbfs ad9644bcpz -80 full 70.4 dbfs ad9644ccpz -80 full 68.6 dbfs ad9644bcpz -155 full 68.7 dbfs f in = 220 mhz 25c 71.1 69.9 dbfs effective number of bits (enob) f in = 10 mhz 25c 11.8 11.5 bits f in = 70 mhz 25c 11.8 11.5 bits f in = 180 mhz 25c 11.6 11.4 bits f in = 220 mhz 2 5c 11.5 11.3 bits worst second or third harmonic f in = 10 mhz 25c ? 94 ? 9 4 dbc f in = 70 mhz 25c ? 92 ? 92 dbc f in = 180 mhz 25c ? 87 ? 92 dbc ad9644bcpz -80 full ? 80 dbc ad9644ccpz -80 full ? 73 dbc ad9644bcpz -155 full ? 80 dbc f in = 220 mhz 25c ? 85 ? 90 dbc spurious - free dynamic range (sfdr) f in = 10 mhz 25c 94 94 dbc f in = 70 mhz 25c 92 92 dbc f in = 180 mhz 25c 87 92 dbc ad9644bcpz -80 full 80 dbc ad9644ccpz -80 full 73 dbc ad9644bcpz -155 full 80 dbc f in = 220 mhz 25c 85 90 dbc worst other (harmonic or spur) f in = 10 mhz 25c ? 98 ? 97 dbc f in = 70 mhz 25c ? 98 ? 9 7 dbc f in = 180 mhz 25c ? 96 ? 95 dbc ad964 4bcpz -80 full ? 90 dbc ad9644ccpz -80 full ? 87 dbc ad9644bcpz -155 full ? 89 dbc f in = 220 mhz 25c ? 95 ? 9 4 dbc ad9644 data sheet rev. c | page 6 of 44 ad9644 - 80 ad9644 - 155 parameter 1 temperature min typ max min typ max unit two - tone sfdr f in = + 3 0 mhz (?7 dbfs ), + 33 mhz (?7 dbfs ) 25c 93 90 dbc f in = + 169 mhz (?7 dbfs ), + 172 mhz (?7 dbfs ) 25c 89 89 dbc crosstalk 2 full ? 105 ? 105 db analog input bandwidth 3 25c 780 780 mhz 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 dbfs on one channel and no input on the alternate cha nnel. 3 analog input bandwidth specifies the ?3 db input bw of the ad9644 input. the usable full - scale bw of the part with good performance is 250 mhz. digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v , maximum sample rate, 1.75 v p - p differential input, vin = ?1.0 dbfs differential input, and dcs enabled, unless otherwise noted. table 3. ad9644 - 80 / ad9644 - 155 parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common - mode bias full 0.9 v differential input voltage full 0.3 3.6 v p - p input voltage range full agnd avdd v input common - mode range full 0.9 1.4 v high level input current ful l ? 100 +100 a low level input current full ? 100 +100 a input capacitance full 4 pf input resistance full 8 10 12 k? sync input logic compliance cmos internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ? 100 +100 a low level input current full ? 100 +100 a input capacitance full 1 pf input resistance full 12 16 20 k? dsync input logic complia nce cmos/lvds internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ? 100 +100 a low level input current full ? 100 +10 0 a input capacitance full 1 pf input resistance full 12 16 20 k? data sheet ad9644 rev. c | page 7 of 44 ad9644 - 80 / ad9644 - 155 parameter temperature min typ max unit logic input (csb) 1 logic compliance cmos high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ? 10 +10 a low l evel input current full 40 132 a input resistance full 26 k ? input capacitance full 2 pf logic input (sclk, pdwn) 2 logic compliance cmos high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current (vin = 1.8 v) full ?92 ?135 a low level input current full ? 10 +10 a input resistance full 26 k ? input capacitance full 2 pf logic input/output (sdio) 1 logic compliance cmos high level inpu t voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ? 10 +10 a low level input current full 38 128 a input resistance full 26 k ? input capacitance full 5 pf digital outputs logic compliance full cml differential output voltage (v od ) full 0.6 0.8 1.1 v output offset voltage (v os ) full 0.75 drvdd/2 1.05 v 1 pull up. 2 pull down. ad9644 data sheet rev. c | page 8 of 44 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, 1.75 v p - p differential input, vin = ?1.0 dbfs differential in put, and dcs enabled, unless otherwise noted. table 4. ad9644 - 80 ad9644 - 155 parameter temperature min typ max min typ max unit clock input parameters input clock rate full 640 640 mhz conversion rate 1 full 40 80 40 155 msps clk period divide - by - 1 mode (t clk ) full 12.5 6.45 ns clk pulse width high (t ch ) divide -by - 1 mode, dcs enabled full 3.75 6.25 8.75 1.935 3.225 4.515 ns divide -by - 1 mode, dcs disabled full 5.95 6.25 6.55 3.065 3.225 3.385 ns di vide - by - 2 mode through divide - by - 8 mode full 0.8 0.8 ns aperture delay (t a ) full 0.78 0.78 ns aperture uncertainty (jitter, t j ) full 0.125 0.125 ps rms data output parameters data output period or ui (unit interval) full 1/(20 f clk ) 1/(20 f clk ) seconds data output duty cycle 25c 50 50 % data valid time 25c 0.78 0.74 ui pll lock time (t lock ) 25c 4 4 s wake up time (standby) 25c 5 5 s wake up time (power - down) 2 25c 2.5 2.5 ms pipeline delay (l atency) full 23 24 23 24 clk cycles data rate per channel (nrz) 25c 1.6 3.1 gbps deterministic jitter 25c 40 40 ps random jitter at 1.6 gbps 25c 9.5 ps rms random jitter at 3.2 gbps 25c 5.2 5.2 ps rms output rise/fall time 25c 50 50 ps termination characteristics differential termination resistance 25c 100 100 ? out - of - range recovery time 25c 2 2 clk cycles 1 conversion rate is the clock rate after the divider. 2 wake - up time is defined as the time required to return to normal operation from power - down mode. data sheet ad9644 rev. c | page 9 of 44 timing specifications table 5. parameter conditions limit sync timing requirements t ssync sync to rising edge of clk+ setup time 0.30 ns typ t hsync sync to rising edge of clk+ hold time 0.30 ns typ spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns min timing diagrams 09180-002 dout+ sample n ? 23 encoded into 2 8b/10b symbols sample n ? 22 encoded into 2 8b/10b symbols sample n ? 21 encoded into 2 8b/10b symbols sample n n ? 22 n ? 23 n ? 21 n ? 20 n + 1 a nalo g input signal clk+ clk? n ? 1 clk+ clk? dout? figure 2. data output timing sync clk+ t hsync t ssync 09180-004 figure 3. sync input timing requirements ad9644 data sheet rev. c | page 10 of 44 absolute maximum rat ings table 6. parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +2.0v vin+a/vin+b, vin?a/vin?b to agnd ? 0.3 v to avdd + 0.2 v clk+, clk? to agnd ? 0.3 v to avdd + 0.2 v sync to agnd ? 0.3 v to avdd + 0.2 v vcma, vcmb to agnd ? 0.3 v to avdd + 0.2 v csb to agnd ? 0.3 v to drvdd + 0.2 v sclk to agnd ? 0.3 v to drvdd + 0.2 v sdio to agnd ? 0.3 v to drvdd + 0.2 v pdwn to agnd ? 0.3 v to drvdd + 0.2 v dout+a, dout0 ? a, dout0+b, dout ? b to agnd ? 0.3 v to drvdd + 0.2 v dsync+a, dsync ? a, dsync+b, dsync ? b to agnd ? 0.3 v to drvdd + 0.2 v environmental operating temperature range (ambient) ? 40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent dama ge to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. thermal characterist ics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the pcb increases the reliability of the solder joints and maximizes the t hermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 unit 48- lead lfcsp 7 mm 7 mm (cp - 48- 8) 0 25 2 14 c/w 1.0 22 c/w 2.5 20 c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - s td 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer pcb with a solid ground plane. as shown table 7 , airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces ja . esd caution data sheet ad9644 rev. c | page 11 of 44 pin configuration and fu nction descriptions 1 2 3 vcma dnc dnc 4 pdwn 5 dnc 6 csb 7 sclk 4 2 d s y n c + a 3 2 d s y n c ? a 2 2 d r v d d 1 2 d r g n d 0 2 d o u t + a 9 1 d o u t ? a 8 1 d o u t + b 7 1 d o u t ? b 6 1 d r g n d 5 1 d r v d d 4 1 d s y n c + b 3 1 d s y n c ? b 4 4 a v d d 5 4 v i n + b 6 4 v i n ? b 7 4 a v d d 8 4 a v d d 3 4 a v d d 2 4 a v d d 1 4 a v d d 0 4 v i n + a 9 3 v i n ? a 8 3 a v d d 7 3 a v d d top view (not to scale) ad9644 25 26 drvdd dnc 27 drgnd 28 avdd 29 sync 30 avdd 31 clk? 32 clk+ 33 avdd 34 dnc 35 avdd 36 vcmb 8 sdio 9 drvdd 10 drvdd 11 drgnd 12 dnc notes 1. dnc = do not connect. 2. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to ground for proper operation. 09180-104 figure 4. lfcsp pin configuration (top view) table 8. pin function descriptions pin no. mnemonic type description adc power supplies 11, 15, 22, 27, 28 drvdd supply digital output driver supply (1.8 v nominal). 2, 4, 7, 9, 37, 38, 41, 42, 43, 44, 47, 48 avdd supply analog power supply (1.8 v nominal). 3, 12, 25, 32, 34, 35 dnc do not connect. 10, 16, 21, 26 drgnd driver ground digital driver supply ground. 0 agnd, exposed pad ground the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pa d must be connected to ground for proper operation. adc analog 40 vin+a input differential analog input pin (+) for channel a. 39 vin?a input differential analog input pin (?) for channel a. 45 vin+b input differential analog input pin (+) for channel b. 46 vin?b input differential analog input pin (?) for channel b. 36 vcma output common-mode level bias output for channel a analog input. 1 vcmb output common-mode level bias output for channel b analog input. 5 clk+ input adc clock inputtrue. 6 clk? input adc clock inputcomplement. digital input 8 sync input input clock divider synchronization pin. 24 dsync+a input active low jesd204a lvds channel a sync inputtrue/jesd204a cmos channel a sync input. 23 dsync?a input active low jesd204a lvds channel a sync inputcomplement. 14 dsync+b input active low jesd204a lvds channel b sync inputtrue/jesd204a cmos channel a sync input. 13 dsync?b input active low jesd204a lvds channel b sync inputcomplement. ad9644 data sheet rev. c | page 12 of 44 pin no. mnemonic type description digital outputs 20 dout+a output channel a cml output data true. 19 dout ? a output channel a cml output data complement. 18 dout+b output channel b cml output data true. 17 dout ? b output channel b cml output data complement. spi control 30 sclk input spi serial clock. 29 sdio input/output spi serial data i nput /o utput . 31 csb input spi chip select (active low). adc configuration 33 pdwn input power - down input. using the spi interface, this input can be configured as power - down or standby. data sheet ad9644 rev. c | page 13 of 44 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, dcs enabled, 1.75 v p - p differential input, vin = ?1.0 dbfs, and 32k sample, t a = 25c, unless otherwise n oted. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 10.1mhz @ ?1dbfs snr = 73.0db (74.0dbfs) sfdr = 95dbc third harmonic 09180-005 figure 5 . ad9644 - 80 single - tone fft with f in = 10.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 30.1mhz @ ?1dbfs snr = 72.7db (73.7dbfs) sfdr = 94dbc second harmonic third harmonic 09180-106 figure 6 . ad9644 - 80 single - tone fft with f in = 30.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 70.1mhz @ ?1dbfs snr = 72.5db (73.5dbfs) sfdr = 94.0dbc second harmonic third harmonic 09180-107 figure 7 . ad9644 - 80 single - tone fft with f in = 70. 1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 140.3mhz @ ?1dbfs snr = 72.2db (73.2dbfs) sfdr = 94.0dbc 09180-108 figure 8 . ad9644 - 80 single - tone fft with f in = 140.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 180.1mhz @ ?1dbfs snr = 71.6db (72.6dbfs) sfdr = 93dbc second harmonic 09180-109 figure 9 . ad9644 - 80 single - tone fft with f in = 180.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 220.1mhz @ ?1dbfs snr = 71.1db (72.1dbfs) sfdr = 92dbc second harmonic third harmonic 09180-110 figure 10 . ad9644 - 80 single - tone fft with f in = 220.1 mhz ad9644 data sheet rev. c | page 14 of 44 0 20 40 60 80 100 120 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 snr/sfdr (dbc/dbfs) input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 09180-111 figure 11 . ad9644 - 80 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 10.1 mhz, f s = 80 msps 0 20 40 60 80 100 120 snr/sfdr (dbc/dbfs) ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 input amplitude (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) sfdr (dbfs) 09180-112 figure 12 . ad9644 - 80 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 180 mhz, f s = 80 msps 65 70 75 80 85 90 95 100 0 50 100 150 200 250 snr/sfdr (dbfs/dbc) input frequenc y (mhz) snr @ ?40c sfdr @ ?40c snr @ +25c sfdr @ +25c snr @ +85c sfdr @ +85c 09180-113 figure 13 . ad9644 - 80 single - tone snr/sfdr vs. input frequency (f in ) and temperature with 1.75 v p - p full - scale, f s = 80 msps 65 70 75 80 85 90 95 100 0 50 100 150 200 250 snr/sfdr (dbfs/dbc) input frequenc y (mhz) snr @ ?40c sfdr @ ?40c snr @ +25c sfdr @ +25c snr @ +85c sfdr @ +85c 09180-114 figure 14 . ad9644 - 80 single - tone snr/sfdr vs. input fre quency (f in ) and temperature with 2.0 v p - p full - scale, f s = 80 msps ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 09180-015 figure 15 . ad9644 - 80 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 29.9 mhz, f in2 = 32.9 mhz, f s = 80 msps ?120 ?100 ?80 ?60 ?40 ?20 0 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 09180-116 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 figure 16 . ad9644 - 80 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 169.1 mhz, f in2 = 172.1 mhz, f s = 80 msps data sheet ad9644 rev. c | page 15 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 29.9mhz @ ?7dbfs 32.9mhz @ ?7dbfs sfdr = 94.4dbc (101.4dbfs) 09180-117 figure 17 . ad9644 - 80 two - tone fft with f in1 = 29.9 mhz and f in2 = 32.9 mh z 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 169.1mhz @ ?7dbfs 172.1mhz @ ?7dbfs sfdr = 91.9dbc (98.9dbfs) 09180-118 figure 18. ad9 644 - 80 two - tone fft with f in1 = 169.1 mhz and f in2 = 172.1 mhz 70 75 80 85 90 95 100 45 50 55 60 65 70 75 80 snr/sfdr (dbfs/dbc) sample r a te (msps) snr channe l b sfdr channe l b snr channe l a sfdr channe l a 09180-119 figure 19 . ad9644 - 80 single - tone snr/sfdr vs. sample rate (f s ) with f in = 70. mhz 0 2000 4000 6000 8000 10,000 12,000 14,000 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 number of hits output code 09180-020 figure 20 . ad9644 - 80 grounded input histogram 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 200 400 600 800 1000 1200 1400 1600 inl error (lsb) output code 09180-121 f igure 21 . ad9644 - 80 inl with f in = 30.3 mhz 0.50 0.25 0 ?0.25 ?0.50 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 dnl error (lsb) output code 09180-122 figure 22 . ad9644 - 80 dnl with f in = 30.3 mhz ad9644 data sheet rev. c | page 16 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-123 155msps 10.1mhz @ ?1dbfs snr = 70.9db (71.9dbfs) sfdr = 94dbc third harmonic figure 23 . ad9644 - 155 single - tone fft with f in = 10.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-124 155msps 30.1mhz @ ?1dbfs snr = 70.8db (71.8dbfs) sfdr = 93dbc third harmonic second harmonic figure 24 . ad9644 - 155 single - tone fft with f in = 30.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-125 155msps 70.1mhz @ ?1dbfs snr = 70.7db (71.7dbfs) sfdr = 92dbc figure 25 . ad9644 - 155 single - tone fft with f in = 70.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-126 155msps 140.1mhz @ ?1dbfs snr = 70.5db (71.5dbfs) sfdr = 92dbc third harmonic second harmonic figure 26 . ad9644 - 155 single - tone fft with f in = 140.1 mhz third harmonic 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-127 155msps 180.1mhz @ ?1dbfs snr = 70.4db (71.4dbfs) sfdr = 92dbc figure 27 . ad9644 - 155 single - tone fft with f in = 180.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-128 155msps 220.1mhz @ ?1dbfs snr = 70.0db (71.0dbfs) sfdr = 90dbc third harmonic figure 28 . ad9644 - 155 single - tone fft with f in = 220.1 mhz data sheet ad9644 rev. c | page 17 of 44 120 100 80 60 40 20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09180-129 snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) figure 29 . ad9644 - 155 single - tone snr/sfdr vs. input amplitu de (a in ) with f in = 10.1 mhz, f s = 80 msps 120 100 80 60 40 20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09180-130 snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) figure 30 . ad9644 - 155 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 180 mhz, f s = 80 msps 100 95 90 80 85 75 70 65 0 50 100 150 200 250 300 input frequency (mhz) snr/sfdr (dbfs/dbc) 09180-131 snr @ ?40c sfdr @ ?40c snr @ +25c sfdr @ +25c snr @ +85c sfdr @ +85c figure 31 . ad9644 - 155 single - tone snr/sfdr vs. inpu t frequency (f in ) and temperature with 1.75 v p - p full - scale, f s = 80 msps 100 95 90 80 85 75 70 65 0 50 100 150 200 250 300 input frequency (mhz) snr/sfdr (dbfs/dbc) 09180-132 snr @ ?40c sfdr @ ?40c snr @ +25c sfdr @ +25c snr @ +85c sfdr @ +85c figure 32 . ad9644 - 155 single - tone snr/sfdr vs. input frequency (f in ) and temperature with 2.0 v p - p full - scale, f s = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09180-133 imd3 (dbc) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) figure 33 . ad9644 - 155 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 29.9 mhz, f in2 = 32.9 mhz, f s = 80 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09180-134 imd3 (dbc) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) figure 34 . ad9644 - 155 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 169.1 mhz, f in2 = 172.1 mhz , f s = 80 msps ad9644 data sheet rev. c | page 18 of 44 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-135 155msps 29.9mhz @ ?7dbfs 32.9mhz @ ?7dbfs sfdr = 89.8dbc (96.8dbfs) figure 35 . ad9644 - 155 two - tone fft with f in1 = 29.9 mhz and f in2 = 32.9 mh z 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50 frequency (mhz) amplitude (dbfs) 09180-136 155msps 169.1mhz @ ?7dbfs 172.1mhz @ ?7dbfs sfdr = 89.1dbc (96.1dbfs) figure 36. ad9644 - 155 two - tone fft with f in1 = 169.1 mhz and f in2 = 172.1 mhz 100 95 90 85 80 75 70 50 65 80 95 110 125 140 155 sample rate (msps) snr/sfdr (dbfs/dbc 09180-137 snr, channel b sfdr, channel b snr, channel a sfdr, channel a figure 37 . ad9644 - 155 single - tone snr/sfdr vs. sample rate (f s ) with f in = 70. mhz 4000 3500 3000 2500 2000 1500 1000 500 0 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 output code number of hits 09180-138 figure 38 . ad9644 - 155 grounded input histogram 0 ?0.2 0.2 ?0.4 0.4 ?0.6 0.6 ?0.8 0.8 ?1 1 0 2000 4000 6000 8000 10000 12000 14000 16000 output code inl error (lsb) 09180-139 figure 39 . ad9644 - 155 inl with f in = 30.3 mhz 0 ?0.25 0.25 ?0.5 0.5 0 2000 4000 6000 8000 10000 12000 14000 16000 output code dnl error (lsb) 09180-140 figure 40 . ad9644 - 155 dnl with f in = 30.3 mhz data sheet ad9644 rev. c | page 19 of 44 equivalent circuits vin avdd 09180-008 figure 41 . equivalent analog input circuit 0.9v 15k? 15k? clk+ clk? avdd avdd avdd 09180-009 figure 42 . equivalent clock input circuit v cm dr vdd douta/b douta/b 4m a 4m a 4m a 4m a r term 09180-089 figure 43 . digital cml output sdio 350? 30k? drvdd 09180-011 figure 44 . equivalent sdio circuit sclk or pdwn 350 ? 30 k? 09180-012 figure 45 . equivalent sclk or pdwn input circuit csb 350 ? 30 k? avdd 09180-014 figure 46 . equivalent csb input circuit avdd avdd 16k? 0.9v 0.9v dsyn c a/b or sync 09180-025 figure 47 . equivalent sync and dsync input circuit ad9644 data sheet rev. c | page 20 of 44 theory of operation the ad9644 dual - core analog - to - digital converter (adc) can be used for divers ity reception of signals, in which the adcs are operating identically on the same carri er but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample any f s /2 frequency segment from dc to 250 mhz, using appropriate low - pass or band - pass filtering at the adc inputs with little loss in adc performance. in nondiversity applications, the ad9644 can be used as a base - band or direct downconversion receiver, in which one adc is used for i input data, and the other is used for q input data. synchronization capability is provided to allow synchro nized timing between multiple devices. programming and control of the ad9644 are accomplished using a 3 - wire spi - compatible serial interface. adc architecture the ad9644 architecture consists of a dual front - end sample - and - hold circuit, followed by a pipe lined, switched - capacitor adc. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to op erate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor digital - to - analog converter (dac) and an interstage re sidue amplifier (mdac). the mdac magnifies the difference between the recon - structed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last s tage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects errors, and passes the dat a to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. during power - down, the output buffers go into a high impedance state. analog input conside rations the analog input to the ad9644 is a differential switched - capacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see figure 48 ). when the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ? of a clock cycle. a small resistor in series with each input can help reduce the peak tr ansient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low - pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, any shunt capacitors or series resistors should be reduced s ince the input sample cap acitor is un buffered . in combination with the driving source impedance, the shun t capacitors limit the input bandwidth . refer to the an - 742 application note, frequency domain response of switched - capacitor adcs ; the an - 827 application note, a reson ant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialog article, transformer - coupled front - end for wideband a/d converters, for more information on this subject (refer to www.analog.com ). c p ar1 c p ar1 c p ar2 c p ar2 s s s s s s c fb c fb c s c s bias bias vin+ h vin? 09180-034 figure 48 . switched - capacitor input for best dynamic performance, the source impedances driving vin+ and vin? should be matched, and the inputs should be differentially balanced. input com mon mode the analog inputs of the ad9644 are not internally dc biased. in ac - coupled applications, the user must provide this bias externally. setting the device so that vcm = 0.5 avdd (or 0.9 v) is recommended for optimum performance. an on - board commo n - mode voltage reference is included in the design and is available from the vcm a and vcmb pin s. using the vcma and vcmb outputs to set the input common mode is recommended. optimum performance is achieved when the common - mode voltage of the analog input i s set by the vcm a and vcmb pin voltage s (typically 0.5 avdd). the vcm a and vcmb pin s must be decoupled to ground by a 0.1 f capacitor. this decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor. data sheet ad9644 rev. c | page 21 of 44 differential input configurations optimum performance is achieved while driving the ad9644 in a differential input configuration. for baseband applications, the ad8138 , ada4937 - 2 , and ada4938 - 2 differential drivers provide excellent performance and a flexible interface to the adc. the output common - mode voltage of the ada4938 - 2 is easily set with the vcm pin of the ad9644 (see figure 49 ), and the driver can be configured in a sallen - key filter topology to provide band limiting of the input signal. vin 76.8? 120? 0.1f 200? 200? 90? avdd 33? 33? 15? 15? 5pf 15pf 15pf adc vin? vin+ vcm ada4938-2 09180-039 figure 49 . differential input configuration using the ada4938 - 2 for baseband applications in which snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 50 . to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9? 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 09180-040 r3 figure 50 . differential tr ansformer - coupled configuration the signal characteristics must be conside red when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noi se performance of most amplifiers is not adequate to achieve the true snr performance of the ad9644. for applications in which snr is a key parameter, differential double balun coupling is the recommended input configuration (see f igure 51 ). in this configuration, the input is ac - coupled and the vcm is provided to each input through a 33 ? resistor. these resistors compensate for losses in the input baluns to provide a 50 ? impedance to the driver. in the double balun and transform er configurations, the value of the input capacitors and resistors is dependent on the input fre - quency and source impedance . based on these parameters the value of the input resistors and capacitors may need to be adjusted or some components may need to b e removed. table 9 displays recommended values to set the rc network for different input frequency ranges . however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note tha t the values given in table 9 are for each r1, r2, c2, and r3 component shown in figure 50 and figure 51 . table 9 . example rc network frequency range (mhz ) r1 series (?) c1 differential (pf) r2 series (?) c2 shunt (pf) r3 shunt (?) 0 to 100 33 8.2 0 8.2 49.9 100 to 250 15 3.9 0 open open an alternative to using a transformer - coupled input at frequencies in the second nyquist zone is to use the ad8376 variable gain amplifier . an example drive circuit including a band - pass filter is shown in figure 52 . see the ad83 76 data sheet for more information. adc r1 0.1f 0.1f 2v p-p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33? 33? s p a p 09180-041 r3 r3 figure 51 . differential double balun input configuration ad9644 data sheet rev. c | page 22 of 44 ad8376 ad9644 1h 1h 1nf 1nf vpos vcm 15pf 68nh 301? 165? 165? 5.1pf 3.9pf 180nh 1000pf 1000pf notes 1. al l induc t ors are coilcraft 0603cs components with the exception of the 1h choke induc t ors (0603ls). 180nh 220nh 220nh 09180-115 figure 52 . differential input configuration using the ad8376 (filter values s hown a re for a 20 mhz bandwidth filter c entered at 140 mhz) volta ge reference a stable and accurate voltage reference is built into the ad9644. the input full scale range can be adjusted through the spi port by adjusting bit 0 through bit 4 of register 0x18. these bits can be used to change the full scale between 1.383 v p - p and 2.087 v p - p in 0.022 v steps, as shown in tabl e 17. clock input consider ations for optimum performance, the ad 9644 sample clock inputs, clk+ and clk?, should be clocked with a differential signal. the signal is typically ac - coupled into the clk+ and clk? pins by means of a transformer or a passive component configuration. these pins are biased internally (see figure 53 ) and require no external bias. if the inputs are floated, the clk? pin i s pulled low to prevent inadvertent clocking. avdd clk+ 2pf 2pf clk? 0.9v 09180-044 figure 53 . equivalent clock input circuit clock input options the ad9644 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. the minimum conversion rate of the ad9644 is 40 msps. at clock rates below 40 msps, dynamic performance of the ad9644 can degrade . figure 54 and figure 55 show two preferred methods for clocking the ad9644 (at clock rates up to 640 mhz). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf balun or an rf transformer. the rf balun configuration is recommended for clock frequencies between 12 5 mhz and 640 mhz, and the rf transformer is recom - men ded for clock frequencies from 4 0 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/balun secondary limit clock excursions into the ad9644 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9644 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1z xfmr 09180-048 figure 54 . transformer - coupled differential clock (up to 200 mhz) 0.1f 0.1f 1nf clock input 1nf 50? clk? clk+ schottky diodes: hsms2822 adc 09180-049 figure 55 . balun - coupl ed differential clock (up to 640 mhz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 56 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 / ad9518 / ad9520 / ad9522 clock drivers offer excellent jitter performance. 100? 0.1f 0.1f 0.1f 0.1f 240? 240? pecl driver 50k? 50k? clk? clk+ clock input clock input ad95xx adc 09180-050 figure 56 . different ial pecl sample clock (up to 640 mhz) data sheet ad9644 rev. c | page 23 of 44 a third option is to ac-couple a differential lvds signal to the sample clock input pins, as shown in figure 57. the ad9510/ ad9511/ad9512/ad9513/ad9514/ad9515/ad9516/ad9517/ ad9518/ad9520/ad9522 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k? 50k ? clk? clk+ clock input clock input ad95xx lvds driver adc 09180-051 figure 57. differential lvds sample clock (up to 640 mhz) in some applications, it may be acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applica- tions, the clk+ pin should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor (see figure 58). optional 100 ? 0.1f 0.1f 0.1f 50 ? 1 1 50 ? resistor is optional. clk? clk+ v cc 1k ? 1k ? clock input ad95xx cmos driver adc 09180-052 figure 58. single-ended 1.8 v cmos input clock (up to 200 mhz) input clock divider the ad9644 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. for divide ratios other than 1 the duty cycle stabilizer is automatically enabled. the ad9644 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. the ad9644 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics. the ad9644 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the perfor- mance of the ad9644. noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs enabled. jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. for inputs near full scale, the degradation in snr from the low frequency snr (snr lf ) at a given input frequency (f input ) due to jitter (t jrms ) can be calculated by snr hf = ?10 log[(2 f input t jrms ) 2 + 10 )10/( lf snr ? ] in the equation, the rms aperture jitter represents the clock input jitter specification. if undersampling applications are particularly sensitive to jitter, as illustrated in figure 59. the measured curve in figure 59 was taken using an adc clock source with approxi- mately 65 fs of jitter, which combines with the 125 fs of jitter inherent in the ad9644 to produce the result shown. 50 55 60 65 70 75 1 10 100 1000 snr (dbfs) input frequency (mhz) 0.05ps 0.2ps 0.5ps 1ps 1.5ps measured 09180-043 figure 59. snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the ad9644. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note (visit www.analog.com ) for more information about jitter performance as it relates to adcs. ad9644 data sheet rev. c | page 24 of 44 channel/chip synchro nization the ad9644 has a sync input that offers the user flexible synchronization options for synchronizing the clock divider. the clock divider sy nc feature is useful for guaranteeing synchro - nized sample clocks across multiple adcs. the input clock divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. the sync input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the sync input signal should be externally syn - chronized to the input clock signal, meeting the setup and hold times shown in table 5 . t he sync input should be driven using a single - ended cmos - type signal. power dissipation an d standby mode as shown in figure 60 and figure 61 , the power dissipated by the ad9644 varies with its sample rate (ad9644 - 80 shown) . the data in figure 60 and figure 61 was taken in jesd204a s erial output mode, using the same operating conditions as those used for the typical performance characteristics . 0 0.05 0.10 0.15 0.20 0.25 0 0.1 0.2 0.3 0.4 0.5 40 50 60 70 80 supp l y current (a) t ot al power (w) encode frequenc y (msps) ia vdd id r vdd t ot al power 09180-144 figure 60 . ad9644 - 80 power and current vs. encode frequency with f in = 10.1 mhz 0.60 0.50 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.40 0.30 0.20 0.10 0 80 90 100 110 120 130 140 150 encode frequency (msps) total power (w) supply current (a) 09180-061 i avdd i drvdd total power figure 61 . ad9644 - 155 power and current vs. encode frequency with f in = 10.1 mhz by asserting pdwn (ei ther through the spi port or by asserting the pdwn pin high), the ad9644 is placed in power - down mode. in this state, the adc typically dissipates 15 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9644 to its normal operating mode. low power dissipation in power - down mode is achieved by shutting down the reference, refe rence buffer, biasing networks, clock , and jesd204a outputs . internal capacitors are discharged when entering power - down mode and then must be recharged when returning to normal operation. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered and t he jesd204a outputs running when faster wake - up times are required . digital outputs jesd204a transmit top level description the ad9644 digital output complies with the jedec standard no. 204a (jesd204a), which describes a serial interface for data converte rs. jesd204a uses 8b/10b encoding as well as optional scrambling. k28.5 and k28.7 comma symbols are used for frame synchronization and the k28.3 control symbol is used for lane synchronization . the receiver is required to lock onto the serial data stream a nd recover the clock with the use of a pll. for details on the output interface, users are encouraged to refer to the jesd204a standard. the jesd204a transmit b lock is used to mul tiplex data from the two analog - to - digital converters onto two independent je sd204a links. each jesd204a link is considered a separate instance of the jesd204a specification, has an independent dsync signal, and contains one or more lanes. note that t he jesd204 specification only allow s one lane per link, while the je sd204a specifi cation adds multi lane support through an alignment procedure. each jesd204a link is described according to the following nomenclature: ? s = s amples transmitted/single converter/frame cycle ? m = n umber of converters/converter device (link) ? l = n umber of lanes /converter device (link) ? n = c onverter r esolution ? n = t otal number of bits per sample ? cf = n umber of control words/frame clock cycle/converter device (link) ? cs = n umber of control bits/conversion sample ? k = n umber of frames per multi frame ? hd = h igh d ensit y m ode ? f = o ctets/ f rame ? c = c ontrol bit (o ver r ange, o verflow, u nderflow) ? t = t ail b it ? scr = s crambler e nable/ d isable ? fchk = c hecksum data sheet ad9644 rev. c | page 25 of 44 figure 62 shows a simplified block diagram of the ad9644 jesd204a l inks. the two l inks each have a primary and a secondary converter input and lane output. by default, the primary i nput 0 of link a is adc converter a and its primary lane o utput 0 is sent on output lane a. the primary i nput 0 of link b is adc converter b and its primary lane o utput 0 i s sent on output lane b. muxes throughout the design are used to enable secondary inputs/outputs and swap lane outputs for othe r configurations. the jesd204a b lock for ad9644 is designed to support the configurations described in t able 10 via a quick configuration register at a ddress 0x5e accessible via the spi bus . in addition to the default mode, the user can program the ad9644 to output both adc chan nels on a single lane (f = 4). this mode allows use of a single high speed data lane, which simplifies board layo ut and connector requirements. in figure 64 the adc a output is represented by w ord 0 and the adc b output by w ord 1. the third output mode utilizes a single link to support both channels. in sing le link mode, the dsynca pin is used to support both outputs. this mode is useful for optimal alignment between the output channels. the 8b/10b encoding works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. by default i n the ad9644, the 14 - bit converter word is broken into two octets. bit 13 through bit 6 are in the first octet. the second octet contains bit 5 through bit 0 and two tail bits. the msb of the tail bits can also be used to indicate an out - of - range condition. the tail bits are configured using the jesd204a link control r egister 1, address 0x60 , bit 6 . the two resulting octets are optionally scrambled and encoded into their corresponding 10 - bit code. the scrambling function is controlled by the jesd204a scrambling and lane c onfiguration register, address 0x06e , bit 7 . figure 63 shows how the 1 4 - bit data is taken from the adc, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10 - bit symbols. figure 63 illustrates the default data format. the scrambler uses a self - synchronizing polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver should be a self - synchronizing version of the scr ambler polynom ial. figure 65 shows the corresponding receiver data path. refer to jedec standard no. 204a - april 2008, section 5.1, for complete transport layer and data format details and section 5.2 for a complete explanation of scrambling and descrambling . ad9644 dual adc jesd204a link a (m = 0, 1, 2; l = 0, 1, 2) converter a sample primary converter input [0] primary lane output [0] secondary converter input [1] secondary lane output [1] jesd204a link b (m = 0, 1, 2; l = 0, 1, 2) secondary converter input [1] secondary lane output [1] primary converter input [0] primary lane output [0] converter b sample a b a b converter b input converter a input lane b lane a lane 0 lane 1 link a ~sync link b ~sync lane mux (spi register 0x5f) lane 1 lane 0 converter a converter b 09180-045 figure 62 . ad9644 transmit link simplified block diagram ad9644 data sheet rev. c | page 26 of 44 table 10. ad9644 jesd204a typical configurations ad9644 configuration jesk204a link a settings jesd204a link b settings comments m = 1; l = 1; s = 1; f = 2 m = 1; l = 1; s = 1; f = 2 max imum sample rate = 80 msps or 155 msps two converters n = 16; cf = 0 n = 16; cf = 0 two jesd204a links cs = 0, 1, 2; k = n/a cs = 0, 1, 2; k = n/a one lane per link scr = 0, 1; hd = 0 scr = 0, 1; hd = 0 m = 2; l = 2; s = 1; f = 2 disabled max imum sample rate = 80 msps or 155 msps two converters n = 16 required for applications needing two aligned samples (i/q applications) one jesd204a link cf = 0; cs = 0, 1, 2 t wo lanes per link k = 16 ; scr = 0, 1; hd = 0 m = 2; l = 1; s = 1; f = 4 disabled max imum sample rate = 80 msps two converters n = 16 one jesd204a link cf = 0; cs = 0, 1, 2 one lane per link k = 8 ; scr = 0, 1; hd = 0 09180-201 data from adc frame assembler (add tail bits) optional scrambler 1 + x 14 + x 15 8b/10b encoder to receiver figure 63 . ad9644 adc output data path 09180-200 word 0[13:6] symbol 0[9:0] word 0[5:0],tail bits[1:0] symbol 1[9:0] word 1[13:6] symbol 2[9:0] word 1[5:0], tail bits[1:0] symbol 3[9:0] time frame 0 frame 1 figure 64 . ad9644 14- bit data transmission with tail bits 09180-202 8b/10b decoder optional descrambler 1 + x 14 + x 15 frame alignment data out from transmitter figure 65 . required receiver data path initial frame synchronization the serial interface must synchronize to the frame boundaries before data can be properly decoded. the jesd204 a standard has a synchronization routine t o identify the frame boundary. when the dsync pin is taken low for at least two clock cycles, the ad9644 enters the code group syn chronization mode. the ad9644 transmits the k28.5 comma symbol until the receiver achieves synchronization . the receiver should then deassert the sync signal (take dsync high) and the ad 9644 begins the initial lane alignment sequence (when enabled th rough bits[3:2] of a ddress 0x60) and subsequently begins transmitting sample data. the first non - k28.5 symbol corresponds to the first octet in a frame . the dsync input can be driven either from a differential lvds source or by using a single - ended cmos driver circuit. the dsync input default to lvds mode but can be set to cmos mode by setting b it 4 in spi a ddress 0x61. if it is driven differentially from an lvds source, the n an external 100 ? termination resistor should be provided. if the dsync input is driven single - ended then the cmos signal should be connected to the dsync+ signal and the dsync ? sig nal should be left disconnected. data sheet ad9644 rev. c | page 27 of 44 table 11. ad9644 jesd204a frame alignment moni toring and correction replacement characters scrambling lane synchronization character to be replaced last octet in multiframe replacement character off on last octet in frame repeated from previous frame no k28.7 (0xfc) off on last octet in frame repeated from previous frame yes k28.3 (0x7c) off off last octet in frame repeated from previous frame not applicable k28.7 (0xfc) on on last octet in frame equals d28.7 (0xfc) no k28.7 (0xfc) on on last octet in frame equals d28.3 (0x7c) yes k28.3 (0x7c) on off last octet in frame equals d28.7 (0x7c) not applicable k28.7 (0xfc) frame and lane alignment mo nitoring and correction frame alignment monitoring and correction is part of the jesd204a specification. the 14-bit word requires two octets to transmit all the data. the two octets (msb and lsb), where f = 2, make up a frame. during normal operating conditions frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. table 11 summarizes the conditions for character insertion along with the expected characters under the various operation modes. if lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters. digital outputs and timing the ad9644 has differential digital outputs that power up by default. the driver current is derived on chip and sets the output current at each output equal to a nominal 4 ma. each output presents a 100 dynamic internal termination to reduce unwanted reflections. a 100 differential termination resistor should be placed at each receiver input to result in a nominal 400 mv peak-to-peak swing at the receiver (see figure 66). alternatively, single-ended 50 termina-tion can be used. when single-ended termination is used, the termination voltage should be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single- ended voltage. the ad9644 digital outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy environments. single point-to-point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of the receiver (that is, the common-mode voltage is 0.9 v for a receiver supply of 1.8 v) if dc-coupled connecting is used (see figure 67). for receiver logic that is not within the bounds of the drvdd supply, an ac-coupled connection should be used. simply place a 0.1 f capacitor on each output pin and derive a 100 differential termination close to the receiver side. if there is no far-end receiver termination or if there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than six inches and that the differential output traces be close together and at equal lengths. 100 ? or 100? differential trace pair dout+x drvdd v rxcm dout?x v cm = rx v cm output swing = 400mv p-p 0.1f 0.1f receiver 09180-093 figure 66. ac-coupled digital output termination example 100 ? 100 ? differential trace pair dout+x drvdd dout?x v cm = drvdd/2 output swing = 400mv p-p receiver 09180-092 figure 67. dc-coupled digital output termination example ad9644 data sheet rev. c | page 28 of 44 ?600 ?200 ?400 0 200 400 600 610 620 0 635 ?0.5 0.5 time (ps) time (ps) uls 400 200 0 ?200 ?400 voltage (mv) height1: eye diagram period1: histogram width@ber1: bathtub 1 ? 20,000 25,000 15,000 10,000 5000 0 hits 615 625 630 10 0 10 ?2 10 ?4 10 ?6 10 ?8 10 ?10 10 ?12 10 ?14 ber 3 + 4 + 09180-094 eye: transition bits offset: ?0.004 uls: 8000; 639999, total: 8000; 639999 0.781 figure 68. ad9644-80 digital outputs data eye, hist ogram and bathtub, external 100 terminations ?300 ?100 ?200 0 100 200 300 305 315 0 330 335 ?0.5 0.5 time (ps) time (ps) uls 500 400 300 200 100 0 ?100 ?300 ?400 ?500 ?200 voltage (mv) height1: eye diagram period1: histogram width@ber1: bathtub 1 ? 45,000 50,000 40,000 35,000 20,000 25,000 30,000 15,000 10,000 5000 0 hits 310 320 325 10 0 10 ?2 10 ?4 10 ?6 10 ?8 10 ?10 10 ?12 10 ?14 ber 3 ? 4 ? 09180-069 0.742 eye: transition bits offset: ?0.004 uls: 8000; 124,0001, total: 8000; 124,0001 figure 69. ad9644-155 digital outputs data eye, hi stogram and bathtub, external 100 terminations figure 68 and figure 69 shows an example of the digital output (default) data eye and a time interval error (tie) jitter histogram. additional spi options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see address 0x15 in table 17). even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. see the memory map section for more details. the format of the output data is twos complement by default. table 12 provides an example of this output coding format. to change the output data format to offset binary or gray code, see the memory map section (address 0x14 in table 17). table 12. digital output coding code (vin+ ) ? (vin? ), input span = 1.75 v p-p (v) digital output twos complement ([d13:d0]) 8191 +0.875 01 1111 1111 1111 0 0.00 00 0000 0000 0000 ?1 ?0.000107 11 1111 1111 1111 ?8192 ?0.875 10 0000 0000 0000 the lowest typical clock rate is 40 msps. for clock rates slower than 60 msps, the user should set bit 3 to 0 in the serial control register (address 0x21 in table 17). this option sets the pll loop bandwidth to use clock rates between 40 msps and 60 msps. setting bit 2 in the output mode register (address 0x14) allows the user to invert the digital samples from their nominal state. as shown in figure 64, the msb is transmitted first in the data output serial stream. data sheet ad9644 rev. c | page 29 of 44 built - in self - test (bist) and ou tput test the ad9644 includes built - in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. a bist (built - in self - test) feature is included that verifies the integrity of the digital d atapath of the ad9644. various output test options are also provided to place predictable values on the outputs of the ad9644. built - in self - test (bist) the bist is a thorough test of the digital portion of the selected ad9644 signal path. when enabled, t he test runs from an internal pseudorandom noise ( pn) source through the digital datapath starting at the adc block output. the bist sequence runs for 512 cycles and stops. the bist signature value for channel a and/ or channel b is placed in register 0x24 and register 0x25. the outputs are not disconnected during this test, so the pn sequence can be observed as it runs. the pn sequence can be continued from its last value or reset from the beginning, based on the value programmed in register 0x0e, bit 2. th e bist signature result varies based on the channel configuration. output test modes digital test patterns can be inserted at various points along the signal path within the ad9644 as shown in figure 70. the ability to inject thes e signals at several locations facilitates debugging of the jesd204a serial communication link. the r egister 0x0d allows test signals generated a t the output of the adc core to be fed directly into the input of the serial link. the output test options ava ilable from r egister 0x0d are shown in table 17. when an output test mode is enabled, the analog section of the adc is discon nected from the digital back end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the seed value f or the pn sequence tests can be forced if the pn reset bits are used to hold the generator in reset mode by setting bit 4 or bit 5 of register 0x0d. these tests c an be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an - 877 application note, interfacing to high speed a dcs via spi . there are nine digital output test pattern options available that can be initiated through the spi (see table 14 for the output bit sequencing options). this feature is useful when validating receiver capture and tim ing. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern selected. note that some patterns do not adhere to the data format select option. in addition, custom user - defined test patterns c an be assigned in the user pattern registers (address 0x19 through address 0x20). the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 (511) bits. a description of the pn sequence short and how it is generated can be found in section 5.1 of the itu - t o.150 (05/96) recommendation. the only difference is that the starting value must be a specific value instead of all 1s (see table 13 for the initial values). the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 (8,388,607) bits. a description of the pn sequence long and how it is generated can be found in section 5. 6 of the itu - t o.150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s (see table 13 for the initial values) and that the ad9644 inverts the bit stream with relation to t he itu - t standard. table 13 . pn sequence sequence initial value first three output samples (msb first) pn sequence short 0x 0092 0x125b , 0x 3c9a , 0x 2660 pn sequence long 0x 3aff 0x3fd7 , 0x 0002, 0x 36e0 the r egister 0x62 allows pa tterns similar to those described in table 14 to be input at different points along the data path. this allows the user to provide predictable output data on the serial link without it having been manipulated by the internal forma tting logic. refer to table 17 for additional information on the test modes available in r egister 0x62. ad9644 data sheet rev. c | page 30 of 44 table 14. flexible output test modes from spi register 0x0d output test mode bit sequence pattern name digital output word 1 (default twos complement format) digital output word 2 (default twos complement format) subject to data format select 0000 off (default) not applic able not applicable yes 0001 midscale short 00 0000 0000 0000 same yes 0010 +full-scale short 01 1111 1111 1111 same yes 0011 ?full-scale short 10 0000 0000 0000 same yes 0100 checkerboard 10 1010 1010 1010 01 0101 0101 0101 no 0101 pn sequence long not applicable not applicable yes 0110 pn sequence short not applicable not applicable yes 0111 one-/zero-word toggle 1111 1111 1111 0000 0000 0000 no 1000 user test mode user data from register 0x19 to register 0x20 user data from register 0x19 to register 0x20 yes 1001 to 1110 not used not appl icable not applicable 1111 ramp output n n + 1 no adc test patterns 14-bit spi register 0x0d bits 3:0 0000 jesd204a sample construction jesd204a test patterns 16-bit spi register 0x62 bits 5:4 = 00 and bits 2:0 000 jesd204a test patterns 10-bit spi register 0x62 bits 5:4 = 01 and bits 2:0 000 frame construction scrambler (optional) 8-bit/10-bit encoder framer seralizer output tail bits adc core 09180-149 figure 70. block diagram showing digital test modes data sheet ad9644 rev. c | page 31 of 44 serial port interface (spi) the ad9644 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see the an-877 application note, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 15). the sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio (serial data input/output) is a dual- purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active-low control that enables or disables the read and write cycles. table 15. serial port interface pins pin function sclk serial clock. the serial sh ift clock input is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active-low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 71 and table 5. other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8-bit words. data can be sent in msb- first mode or in lsb-first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09180-152 figure 71. serial port interface timing diagram ad9644 data sheet rev. c | page 32 of 44 hardware interface the pins described in table 15 comprise the physical interface between the user programming device and the serial port of the ad9644. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note, micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9644 to prevent these signals from transi - tioning at the converter inputs during critical sampling periods. spi accessible featu res table 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note, interfacing to high speed adcs via spi . the ad9644 part - specific features are described in detail in the memory map register descriptions section . table 16 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits full scale allows the user to set the input full scale voltage jesd204a allows user to configure the jesd204a output data sheet ad9644 rev. c | page 33 of 44 memory map reading the memory m ap register table each row in the memory map register table has eight bit locations . the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); the adc functions regi sters, including setup, control, and test (address 0 x08 to address 0x3a ) ; and the jesd204a configuration registers (address 0x5e to address 0x79) . the memory map register table (see table 17 ) lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x18, the input span select register, has a hexadecimal default value of 0x00. this means that bit 0 throu gh bit 4 = 0, and the remaining bits are 0s. this setting is the default reference selection setting. the default value uses a 1.75 v p - p reference. for more information on this function and others, see the an - 877 application note, interfacing to high speed adcs via spi. this application note details the functions con - trolled by register 0x00 to register 0xff. open locations all address and bit locations that are not included in table 17 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the ad9644 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table , table 17. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or wr iting logic 0 for the bit. transfer register map address 0x08 through address 0x79 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allo ws these registers to be updated internally and simulta neously when the transfer bit is set. the internal update takes place when the transfer bit is set, and the bit autoclears. channel - specific registers some channel setup functions, such as the channel output mode , can be programmed differently for each adc or link channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 17 as local. these l ocal registers and bits can be accessed by setting the appropriate channel a /link a or channel b /link b bits in register 0x05. if both bits are set in register 0x05 , the subsequent write affects the registers of both channels/links. in a spi read cycle, o nly channel a /link a or channel b /link b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a /link a . registers and bits designated as global in tab le 17 affect the entire part or the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits. ad9644 data sheet rev. c | page 34 of 44 memory map register table all address and bit locations that are not included in table 17 are not currently supported for this device. table 17 . memory map registers addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default/ comments chip configuration registers 0x00 spi port configuration (global) 1 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 nibbles are mirrored so that lsb - first or msb - first mode is set correctly, regardless of shift mode. to co ntrol this register, all channel index bits in register 0x05 must be set. 0x01 chip id (global) 8 - bit chip id[7:0] (ad9644 = 0x7e) (default) 0x7e read only 0x02 chip grade (global) open open speed grade id 00 = 80 msps 10 = 155 msps open open open open speed grade id differentiate s devices; read only channel index and transfer registers 0x05 channel index (global) open open open open open open adc b and link b (default) adc a and link a (default) 0x03 bits set to determine which device on the chip rec eives n ext write command; local registers only 0xff transfer (global) open open open open open open open transfer 0x00 synchro - nously transfers data from master shift register to slave adc functions 0x08 power modes (local) open open external power - down pin function (local) 0 = power - down 1 = standby open open open internal power - down mode (local) 00 = normal operation 01 = full power - down 10 = standby 11 = reserved 0x00 determines various generic modes of chip operation 0x09 global clock (global) open open open open open open open duty cycle stabilizer (default) 0x01 0x0a pll s tatus (global) pll locked open open open open open open open 0x00 read only 0x0b clock divide (global) open open input clock divider phase adjust 000 = no delay 001 = 1 input c lock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divi de by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 automatically cause s duty cycle stabilizer to become active data sheet ad9644 rev. c | page 35 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default/ comments 0x0d test mode (local) user test mode c ontrol 0 = continuo us/repeat p atter n 1 = single p attern open reset pn long gen erator reset pn short gen erat or output test mode 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn long sequence 0110 = pn short sequence 01 11 = one/zero word toggle 1000 = user test m ode 1001 to 1110 = u nused 1111 = ramp o utput 0x00 when this register is set, test data is used in place of normal adc data 0x0e bist enable (global) open open open open open reset bist sequence open bist enable 0x00 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode open open open output d isable (local) open output invert (local) output format 00 = offset binary 01 = twos complement (defa ult) 10 = gray code 11 = offset binary (local) 0x01 configures outputs and the format of the data 0x15 output a djust ( g lobal) open open open open open open output drive level adjust 11 = 320 mv 00 = 400 mv 10 = 440 mv 01 = 500 mv 0x00 0x18 input s pan se lect (global) open open open full - scale input voltage s election 01111 = 2.087 v p - p 00001 = 1.772 v p - p 00000 = 1.75 v p - p (default) 11111 = 1.727 v p - p 10000 = 1.383 v p - p 0x00 full - scale input adjustment in 0.022 v steps 0x19 user test pattern 1 lsb (global) user test pattern 1 [7:0] 0x00 0x1a user test pattern 1 msb (global) user test pattern 1 [15:8] 0x00 0x1b user test pattern 2 lsb (global) user test pattern 2 [7:0] 0x00 0x1c user test pattern 2 msb (global) user test pattern 2 [15:8] 0x00 0x1d user test pattern 3 lsb (global) user test pattern 3 [7:0] 0x00 0x1e user test pattern 3 msb (global) user test pattern 3 [15:8] 0x00 0x1f user test pattern 4 lsb (global) user test pattern 4 [7:0] 0x00 0x20 user test pattern 4 msb (global) us er test pattern 4 [15:8] 0x00 0x21 pll control (global) open open open open pll low e ncode r ate e nable open open open 0x00 bit 3 must be enabled if adc clock rate is less than 60 msps ad9644 data sheet rev. c | page 36 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default/ comments 0x24 bist signature lsb (local) bist signature[7:0] 0x00 read only 0 x25 bist signature msb (local) bist signature[15:8] 0x00 read only 0x3a sync control (global) open open open open open clock divider next sync only clock divider sync enable master sync buffer enable 0x00 jesd204a configuration registers 0x5e jesd204a quick configure (global) open open open open open 000 = default configuration determined by other registers 001 = two converters using two links with one lane per link 010 = two converters using one link with two lanes per link 011 = two converters using one link and a single lane 100 to 111: reserved 0x00 changes settings of address 0x5f to address 0x60 and address 0x6e to address 0x72 (self clearing) 0x5f jesd204a lane assignment (global) open open open open jesd204a serial lane control 0000 = one lane per link . link a : lane 0 sent on lane a , link b : lane 0 sent on lane b 0001 = one lane per link . link a : lane 0 sent on lane b , link b : lane 0 sent on lane a. 0010 = two lanes per link . link a : lane 0, lane 1 s ent on lane a, lane b . lin k b disabled . 0011 = two lanes per link . link a : lane 0, lane 1 s ent on lane b, lane a. link b disabled. 0100 = two lanes per link . link b : lane 0, lane 1 s ent on lane a, lane b. link a disabled . 0101 = two lanes per link . link b : lane 0, 1 s ent on lane b, lane a. link a disa bled . 0110 to 1111: reserved 0x00 0x60 jesd204a link control register 1 (local) open serial tail bit enable serial test sample enable serial lane synchro nization enable serial lane alignment sequence mode 00 = disabled 01 = enabled 10 = reserved 11 = alw ays on test mode frame alignment character insertion disable serial transmit link powered down 0x00 0x61 jesd204a link control register 2 (local) local dsync mode 00 = individual mode 01 = global mode 10 = dsync active mode 11 = dsync pin disabled dsync pin input inverted cmos dsync input 0 = lvds 1 = cmos open bypass 8b/10b encoding invert transmit bits mirror serial output bits 0x00 0x62 jesd204a link control register 3 (local) disable chksum open link test generation input selection 00 = 16 - bit data injected at sample input to the link 01 = 10 - bit data injected at output of 8b/10b encoder 10 = reserved 11 = reserved open link test generation mode 000 = normal operation 001 = alternating checker board 010 = 1/0 word toggle 011 = pn sequence long 100 = pn sequence short 101 = user test pattern data continuous 110 = user test pattern data single 111 = ramp output 0x00 0x63 jesd204a link control register 4 (local) initial lane assignment sequence repeat count 0x00 0x64 jesd204a device identification n umber (did) (local) jesd204a serial device identification (did) number 0x00 data sheet ad9644 rev. c | page 37 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default/ comments 0x65 jesd204a bank identification number (bid) (local) open open open open jesd204a serial bank identification number (bid) 0x00 0x66 jesd204a lane identification number (lid) for lane 0 (local) open open open jesd204a serial lane identification (lid) number for lane 0 0x00 0x67 jesd204a lane identification number (lid) for lane 1 (local) open open open jesd204a serial lane identification (lid) number for lane 1 0x01 0x6e jesd204a scrambler (scr) and lane (l) configuration register enable serial scrambler mode (scr) ( l ocal) open open open open open open lane control (global) 0 = one lane per link (l = 1) 1 = two lanes per link (l = 2) 0x80 0x6f jesd204a number of octets per frame (f) (global) jesd204a number of octets per frame (f) these bits are calculated based on the equation: f = m (2 l) 0x01 read only 0x70 jesd204a number of frames per multiframe (k) (l ocal) open open open jesd204a number of frames per multifram e (k) 0x0f 0x71 jesd204a number of converters per link (m) (global) open open open open open open open number of converters per link (m) 0 = link connected to one adc (m = 1) 1 = link connected to two adcs (m = 2) 0x00 0x72 jesd 204a adc resolution (n) and control bits per sample (cs) (local) number of control bits per sample (cs) 00 = no control bits (cs = 0) 01 = one control bit (cs = 1) 10 = two control bits (cs = 2) 11 = unused open converter resolution (n) (read only) 0x4d 0x73 jesd204a total bit s per sample (n) (global) open open open total bits per sample (n) (read only) 0x0f read only 0x74 jesd204a samples per converter (s) frame cycle (global) open open open samples per converter (s) frame cycle (read only) always 1 for the ad9644 0x00 read only 0x75 jesd204a hd and cf config uration (global) enable high density format (hd = 0, read only ) open open number of control words per frame clock cycle per link (cf) C always 0 for the ad9644 (read only) 0x00 read only ad9644 data sheet rev. c | page 38 of 44 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default/ comments 0x76 jesd204a serial reserved f ield 1 (res1) serial reserved field 1 (res1) C these registers are available for customer use 0x00 0x77 jesd204a serial reserved field 2 (res2) serial reserved field 2 (res2) C these registers are available for customer use 0x00 0x78 jesd204a checksum value (fchk) for lane 0 (l ocal) serial checksum value for lane 0 (fchk) 0x00 read only 0x79 jesd204a checksum value (fchk) for lane 1 (local) serial checksum value for lane 1 (fchk) 0x00 read only 1 the channel index register at address 0x05 should be set to 0x03 (default) when writing to address 0x00. memory map register descriptions for additional informat ion about functions controlled in register 0x00 to register 0x25, see the an - 877 application note, interfacing to high speed adcs via spi . sync control (register 0x3a) bits[7:3] open bit 2 clock divider next sy nc only if the master sync buffer enable bit (address 0x 3a , bit 0) and the clock divider sync enable bit (address 0x 3a , bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. the clock divider sy nc enable bit (address 0x 3a , bit 1) resets after it syncs. bit 1 clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0 master sync buffer enable bit 0 must be high to enable any of the sync functions. if the sync capability is not used this bit should remain low to conserve power. jesd204a quick configure (register 0x5e) bits[7:3] reserved bits [2:0] register quick configuration wr ite s to bits [2:0] of this register configure the part for the most popular modes of operation for the jesd204a link. the intent of this register is to simplify the part setup for typical serial link operation modes. writing values other than 0x0 to this regis ter causes registers throughout the jesd 204a memory map to be updated. once these registers have been written the affected jesd204a configuration register read s back with their new values and can be updated. these bits are self clearing and always read bac k as 0b000. 000: d efault configuration determined by other registers 001: t wo c onverters using t wo l inks with one l ane per l ink ( m ax imum s ample rate = 80 mhz or 155 mhz) each link configuration: m = 1; n = 16; cf = 0; k = 16; s = 1; f = 2; l = 1; hd = 0; 010 = t wo c onverters using one l ink with two l anes per l ink (max imum s ample rate = 80 mhz or 155 mhz) . each link configuration: m = 2; n = 16; cf = 0; k = 16; s = 1; f = 2; l = 2; hd = 0; u s es dsynca pin for synchronization. setting this mode sets a ddress 0x5f = 0x02 and sets a ddress 0x60 = 0x14 for link a and sets a ddress 0x60 = 0x01 for link b . 011 = t wo c onverters using o ne l ink and a single l ane ( m ax i - mum s ample rate = 78.125 mhz) . each link configuration: m = 2; n = 16; cf = 0; k = 8;s = 1; f = 4; l = 1; hd = 0; u s es dsynca pin for synchronization and douta for output signals. 100 to 111: r eserved . jesd204a lane assignment (register 0x5f) bits[7:4] reserved bits [3:0] jesd204a serial lane control these bits set the lan e usage. see figure 62. 0000: o ne l ane per l ink. link a : lane 0 s ent on lane a, link b : lane 0 s ent on lane b. 0001: one lane per l ink . link a : lane 0 s ent on lane b, link b : lane 0 s ent on lane a. 0010: t wo l anes per l ink. link a : lane 0, one s ent on l ane a, link b disabled. 0011: t wo l anes per l ink. link a : lane 0, one s ent on lane b, lane a. link b disabled. 0100: t wo l anes per l ink. link b : lane 0, one s ent on lane a, lane b. link a disabled. 0101: two l anes per l ink. link b : lane 0, one s ent on lan e b, lane a. link a disabled. 0110 to 1111: r eserved for future use. data sheet ad9644 rev. c | page 39 of 44 jesd204a link control register 1 (register 0x60) bit 7 reserved bit 6 serial tail bit enable if this bit is set, the unused tail bits are padded with a p s eudo random number s equence from a 31 - bit lfsr (see jesd204a 5.1.4). bit 5 serial test sample enable if this bit is set , jesd204a t est s amples are enabled transport layer t est s ample s equence (as specified in jesd204a section 5.1.6.2) is sent on all link lanes. bit 4 serial lane synchroni zation enable if th is bit is set , l ane s ynchronization is enable d. both sides perform lane sync. f rame a lignment c haracter i nsertion uses either /k28.3/ or /k28.7/ control characters (see jesd204a 5.3.3.4) . bit s [3:2] serial lane alignment sequence mode 00: initial lane alignment sequence d isabled. 01: initial lane alignment sequence enabled. 10: r eserved. 11: i nitial l ane a lignment s equence always on t est mode jesd204a d ata l ink l ayer t est m ode where repeated lane alignment sequence is sent on all lanes. bi t 1 frame alignment character insertion dis able if b it 1 is set , the f rame a lignment c haracter i nsertion is disabled per jesd204a section 5.3.3.4. b it 0 serial transmit link power ed down if b it 0 is set high , the serial transmit link is held in reset with its clock gated off. the jesd204a transmitter should be powered down when changing any of the l ink c onfiguration b its. jesd204a link control register 2 (register 0x61) bits[7:6] local d sync mode 00: i ndiv idual/separate m ode. each link is controlled by a s eparate dsync pin that independently controls code group synchronization. 01: global m ode. any dsync signal cause s the link to begin code group synchronization. 10: sync active m ode. dsync signal is active force code group synchronization. 11: dsync p in d i sabled. bit 5 d sync pin input i nvert ed if this bit is set, the dsync pin of the link is inverted (active high). bit 4 cmos dsync input 0: lvds d ifferential p air dsync i nput (default) 1: cmos s ingle e nded dsync i nput bit 3 open bit 2 bypass 8b/10b encoding if this bit is set the 8b/10b encoding is bypassed and the most significant bits are set to 0. bit 1 invert transmit bits setting this bit inverts the 10 serial output bits. this effectively inverts the output signals. bit 0 mirror serial output bits sett ing this bit reverses the order of the 10b outputs. jesd204a link control register 3 (register 0x62) bit 7 disable chksum setting this bit high disables the chksum configuration parameter (f or testing purposes only) . bit 6 open bit s[5: 4 ] link test generati on input selection 0 0 : 16- bit test g eneration d ata injected at sample input to the link . 01: 10- bit t est g eneration d ata injected at output of 8b/10b encoder (at input to phy) . 10: r eserved . 11: r eserved . bit 3 open bits [2:0] link test generation mode 000: n ormal o peration (test mode disabled) . 001: a lternating c hecker b oard . 010: 1/0 w ord t oggle . 011: pn s equence l ong . 100: pn s equence s hort . 101: c ontinuous/ r epeat u ser t est m ode m ost significant bits from user p attern (1, 2, 3, 4) placed on the output fo r 1 clock cycle and then repeat. (output user p attern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 ) . 110: s ingle u ser t est m ode m ost significant bits from u ser p attern (1, 2, 3, 4) placed on the output for 1 clock cycle and then output all zeros. ( o utput u ser p atte rn 1, 2, 3, 4, then output all zeros). 111: r amp o utput . jesd204a link control register 4 (register 0x63) bits [7:0] initial lane alignment sequence repeat count spe cifies the number of times the initial l ane a l ignment s equence (ilas) is repeated. if 0 is p rogrammed the ilas does not repeat . if 1 is programmed the ilas repeat one time and so on. see r egister 0x60 , b its[ 3:2 ] to enable the ilas and for a test mode to continuously enable the initial lane alignment sequence. ad9644 data sheet rev. c | page 40 of 44 jesd204a device identification number (did) (register 0x64) bits [7:0] serial device identification (did) number jesd204a bank identification number (bid) (register 0x65) bits [7:4] open bits [3:0] serial bank identification (did) number jesd204a lane identification number (lid) for lane 0 (regi ster 0x66) bits [7:5] open bits [4:0] serial lane identification (lid) n umber for lane 0. jesd204a lane identification number (lid) for lane 1 (register 0x67) bits [7:5] open bits [4:0] serial lane identification (lid) n umber for lane 1. jesd204a scrambler (sc r) and lane configuration registers (register 0x6e) bit 7 enable serial scrambler mode setting this bit high enables the s crambler (scr = 1). bits [6: 1 ] open bit [ 0 ] serial lane control. 0 0000: o ne l ane per l ink (l = 1). 00001 : t wo l anes per l ink (l = 2). 00010: 11111 r eserved . jesd204a number of octets per frame (f) (register 0x6f read only) bits [7:0] number of octets per frame (f) the readback from this register is calculated from the following equation: f = (m 2)/ l valid values for f for the ad9644 are: f = 2, with m = 1 and l = 1 f = 4, with m = 2 and l = 1 f = 2 , with m = 2 and l = 2 jesd204a number of frames per multiframe (register 0x70) bits [7:5] reserved bits [4:0] number of f rames per m ultiframe (k). jesd204a number of converters per link (m) (register 0x71) bits [7:1] reserved bit 0 number of c onverters per l ink per d evice (m). 0 : l ink connected to one adc. only primary input used (m = 1 ). 1 : l ink connected to two adcs. primary and secondary inputs used (m = 2). jesd204a adc resolution (n) and control bits per sample (cs) (register 0x72) bits [7:6] number of c ontrol b its per s ample (cs) 00: n o control bits sent per sample (cs = 0) . 01: o ne control bits sent per sample overr ange b it e nabled. (cs = 1) . 10: t wo control bits sent per sample o v erflow / u nderflow b its e nabled (cs = 2) . 11: u nused . bit 5 open bits [4:0] converter r esolution (n) read only bits showing the converter resolution (reads back 1 3 (0xd) for 14 - bit resolution ). jesd204a total bits per sample (n) (register 0x73) bits [7:5] open bits [4:0] total number of b its per s ample (n) read only bits showing the total number of bits per sample 1 (reads back 15 (0xf) for 16 bits per sample). jesd204a samples per converter (s) frame cycle (register 0x74) bits [7:5] open bits [4:0] samples per conver ter frame cycle (s) read only bits showing the number of samples per converter frame cycle ? 1 (reads back 0 (0x0) for 1 sample per converter frame). jesd204a hd and cf configuration (register 0x75) bit 7 enable high density format (read only) read only bit always 0 in the ad9644 . bits [ 6 :5] reserved bits [4:0] numbe r of control words per frame c lo ck c ycle per l ink ( cf ) read only bits reads back 0x0 for the ad9644. data sheet ad9644 rev. c | page 41 of 44 jesd204a serial reserved field 1 (register 0x76) bits [7:0] serial reserved field 1 (res1) this read/write register is available for customer use. jesd204a serial reserved field 2 (re gister 0x77) bits [7:0] serial reserved field 2 (res2) this read/write register is available for customer use. jesd204a serial checksum value for lane 0 (register 0x78) bits [7:0] serial checksum value for lane 0 this read only register is automatically cal culated for each lane. sum (all link configuration parameters for lane 0) mod e 256. jesd204a serial checksum value for lane 1 (register 0x79) bits [7:0] serial checksum value for lane 1 this read only register is automatically calculated for each lane. sum (all link configuration parameters for lane 1) mod e 256. ad9644 data sheet rev. c | page 42 of 44 applications informa tion design guidelines before starting design and layout of the ad9644 as a system, it is recommended that the designer become familiar with these guidelines, which discuss th e special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the ad9644, it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd s everal different decoupling capa - citors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. a single pcb ground plane should be sufficient when using the ad9644. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane o n the pcb should mate to the ad9644 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. for detailed information about packaging and pcb layout of chip scale packages, see the an - 772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . vcma and vcmb the vcm a and vcmb pin s should be decoupled to ground with a 0.1 f capacitor, as shown in figure 50. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9644 to keep these signals from transitioning at the converter inputs during critical sampling periods. data sheet ad9644 rev. c | page 43 of 44 outline dimensions * compliant to jedec standards mo-220-vkkd-2 with exception to exposed pad dimension. forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 48 12 13 37 36 24 25 * 5.55 5.50 sq 5.45 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 exposed pad (bottom view) 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max top view 0.60 max 0.60 max pin 1 indicator 0.50 ref pin 1 indicator 0.22 min 7.10 7.00 sq 6.90 6.85 6.75 sq 6.65 02-23-2010-c figure 72. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-8) dimensions shown in millimeters ordering guide model 1 1 f11f 1 temperature range package description package option ad9644bcpz-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644bcpzrl7-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644ccpz-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644ccpzrl7-80 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644bcpz-155 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644bcpzrl7-155 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9644-80kitz evaluation board AD9644-155KITZ evaluation board 1 z = rohs compliant part. ad9644 data sheet rev. c | page 44 of 44 notes ? 2010 C 2012 analog d evices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09180 - 0- 1/12(c) |
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